View AK4121A10_6489914.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

[ak4121a] ms0337-e-06 2010/04 - 1 - general description the ak4121a is a stereo asynchronous sample rate converter. the input sample rate ranges from 8khz to 96khz. the output sample rate is 32khz, 44.1khz, 48khz or 96khz. since the internal pll eliminates the need for a master clock in slav e mode, the ak4121 simplifie s the system design. therefore, the ak4121a is suitable fo r applications requiring multiple sa mple rates, such as car audio, dvd recorders, and digital audio recording. features ? stereo asynchronous sample rate converter ? input sample rate range (fsi): 8khz to 96khz ? output sample rate (fso ): 32khz/44.1khz/48khz/96khz ? input to output sample rate ratio: fso/fsi = 0.33 to 6 ? thd+n: ?113db ? i/f format: msb justified, lsb justified (24/20/16bit) and i 2 s ? clock for master m ode: 256/384/512/768fso ? de-emphasis filter: 32khz/44.1khz/48khz ? src bypass mode ? soft mute function ? power supply: vdd: 3.0 to 3.6v, tvdd: 3.0 to 5.5v (for input tolerant) ? ta: ?40 to +85 c serial a udio i/f sample rate converter serial a udio i/f ilrc k ibick sdti olrck obick sdto (mclk) pdn idif1 vdd dvss pll de-em filter dem0 dem1 idif0 odif1 odif0 idif2 cmode0 smute cmode1 avss filt tvdd cmode2 soft mute asynchronous sample rate converter ak4121a
[ak4121a] ms0337-e-06 2010/04 - 2 - ordering guide ak4121avf ? 40 +85 c 24pin vsop (0.65mm pitch) akd4121a evaluation board for ak4121a pin layout difference between ak4121 and ak4121a the ak4121a has a better performance than the ak4121 regarding of the tracking capability to the change of the input sampling frequency (fsi) which normally takes long se ttling time. refer to ?tracking to the input sampling frequency?. 6 5 4 3 2 1 filt avss smute pdn dem0 dem1 ilrck 7 ibick 8 vdd dvss tvdd mclk olrck obick sdto odif1 top view 10 9 sdti idif0 idif1 11 idif2 12 odif0 cmode2 cmode1 cmode0 19 20 21 22 23 24 18 17 15 16 14 13
[ak4121a] ms0337-e-06 2010/04 - 3 - pin/function no. pin name i/o function 1 filt o loop-filter pin for pll 2 avss i analog ground pin 3 pdn i power-down pin when ?l?, the ak4121a is powered-down and reset. 4 smute i soft mute pin 5 dem0 i de-emphasis filter control pin #0 6 dem1 i de-emphasis filter control pin #1 7 ilrck i l/r clock pin for input 8 ibick i audio serial data clock pin for input 9 sdti i audio serial data input pin 10 idif0 i input data format pin #0 11 idif1 i input data format pin #1 12 idif2 i input data format pin #2 13 cmode0 i clock mode select pin #0 14 cmode1 i clock mode select pin #1 15 cmode2 i clock mode select pin #2 16 odif0 i output data format pin #0 17 odif1 i output data format pin #1 18 sdto o audio serial data output pin 19 obick i/o audio serial data clock pin for output 20 olrck i/o l/r clock pin for output 21 mclk i master clock pin for output 22 tvdd i input buffer power supply pin, 3.3v or 5v 23 dvss i digital ground pin 24 vdd i power supply pin, 3.3v
[ak4121a] ms0337-e-06 2010/04 - 4 - absolute maximum ratings (avss=dvss=0v; note 1 ) parameter symbol min max units power supplies: core input buffer |avss-dvss| ( note 1 ) vdd tvdd gnd ? 0.3 ? 0.3 4.6 6.0 0.3 v v v input current, any pin except supplies iin - 10 ma input voltage vin ? 0.3 tvdd+0.3 v ambient temperature (power applied) ta ? 40 85 c storage temperature tstg ? 65 150 c note 1. all voltages with respect to ground. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (avss=dvss=0v; note 2 ) parameter symbol min typ max units power supplies: core input buffer vdd tvdd 3.0 vdd 3.3 5 3.6 5.5 v v note 2. all voltages with respect to ground. src performance (ta= ? 40 85 c; vdd=3.0 3.6v; tvdd=3.0~5.5v; data=20bit; measurement bandwidth=20hz~fso/2; unless otherwise specified.) parameter symbol min typ max units resolution 20 bits input sample rate fsi 8 96 khz output sample rate fso 32 96 khz dynamic range (input= 1khz, ? 60dbfs, note 3 ) fso/fsi=44.1khz/48khz fso/fsi=48khz/44.1khz fso/fsi=32khz/48khz fso/fsi=96khz/32khz worst case (fso/fsi=48khz/96khz) dynamic range (input= 1khz, ? 60dbfs, a-weighted, note 3) fso/fsi=44.1khz/48khz - - - - 112 - 114 114 114 115 - 117 - - - - - - db db db db db db thd+n (input= 1khz, 0dbfs, note 3) fso/fsi=44.1khz/48khz fso/fsi=48khz/44.1khz fso/fsi=32khz/48khz fso/fsi=96khz/32khz worst case (fso/fsi=48khz/8khz) - - - - - ? 113 ? 112 ? 113 ? 111 - - - - - ? 103 db db db db db ratio between input and output sample rate (fso/fsi, note 4, note 5) fso/fsi 0.33 6 - note 3. measured by rohde & schwarz upd0 4, rejection filter= wide, 8192point fft. note 4. the ?0.33? is the ratio of fso/fsi when fsi is 96khz and fso is 32khz note 5. the ?6? is the ratio when fsi is 8khz and fso is 48khz.
[ak4121a] ms0337-e-06 2010/04 - 5 - digital filter (ta= ? 40 85 c; vdd=3.0 3.6v; tvdd=3.0~5.5v) parameter symbol min typ max units digital filter 0.985 fso/fsi 6.000 pb 0 0.4583fsi khz 0.905 fso/fsi < 0.985 pb 0 0.4167fsi khz 0.714 fso/fsi < 0.905 pb 0 0.3195fsi khz 0.656 fso/fsi < 0.714 pb 0 0.2852fsi khz 0.536 fso/fsi < 0.656 pb 0 0.2245fsi khz 0.492 fso/fsi < 0.536 pb 0 0.2003fsi khz 0.452 fso/fsi < 0.492 pb 0 0.1781fsi khz passband ? 0.001db 0.333 fso/fsi < 0.452 pb 0 0.1092fsi khz 0.985 fso/fsi 6.000 sb 0.5417fsi khz 0.905 fso/fsi < 0.985 sb 0.5021fsi khz 0.714 fso/fsi < 0.905 sb 0.3965fsi khz 0.656 fso/fsi < 0.714 sb 0.3643fsi khz 0.536 fso/fsi < 0.656 sb 0.2974fsi khz 0.492 fso/fsi < 0.536 sb 0.2732fsi khz 0.452 fso/fsi < 0.492 sb 0.2510fsi khz stopband 0.333 fso/fsi < 0.452 sb 0.1822fsi khz passband ripple pr 0.01 db stopband attenuation sa 96 db group delay ( note 6 ) gd - 57.5 - 1/fs note 6. this value is the time from the rising edge of lrck after data is input to rising edge of lrck after data is output, when lrck for output data corresponds with lrck for input.(at 20bit msb justified, 16bit and 20bit lsb justified) dc characteristics (ta= ? 40 85 c; vdd=3.0~3.6v; tvdd=3.0~5.5v) parameter symbol min typ max units power supply current (vdd+tvdd) normal operation: fsi=fso=48khz at sl ave mode: vdd=tvdd=3.3v fsi=fso=96khz at master mode: vdd=tvdd=3.3v : vdd=tvdd=3.6v power down: pdn = ?l? ( note 7 ) 10 20 10 - - 40 100 ma ma ma a high-level input voltage low-level input voltage vih vil 0.7xvdd - - - - 0.3xvdd v v high-level output voltage (iout= ? 400 a) low-level output voltage (iout=400 a) voh vol vdd-0.4 - - - - 0.4 v v input leakage current iin - - 10 a note 7. all digital inputs including clock pins are held dvss.
[ak4121a] ms0337-e-06 2010/04 - 6 - switching characteristics (ta= ? 40 85 c; vdd=3.0~3.6v; tvdd=3.0~5.5v; c l =20pf) parameter symbol min typ max units master clock input (mclk) frequency duty cycle fclk dclk 8.192 40 - - 36.864 60 mhz % l/r clock for input data (ilrck) frequency duty cycle fs duty 8 48 50 96 52 khz % l/r clock for output data (olrck) frequency ( note 8 ) fs 32 96 khz duty cycle slave mode duty 48 50 52 % master mode duty 50 % audio interface timing input ibick period ibick pulse width low ibick pulse width high ilrck edge to ibick ? ? ( note 9) ilrck frequency = 8khz ~ 32khz ilrck frequency = 32khz ~ 48khz ilrck frequency = 48khz ~ 96khz bick ? ? to ilrck edge ( note 9) sdti hold time from ibick ? ? sdti setup time to ibick ? ? tbck tbckl tbckh tlrb tlrb tlrb tblr tsdh tsds 1/64fs 65 65 1/256fs+45 1/256fs+25 1/256fs+15 30 30 30 16/256fs 16/256fs 16/256fs ns ns ns ns ns ns ns ns ns output (slave mode) obick period obick pulse width low obick pulse width high olrck edge to obick ? ? ( note 9) obick ? ? to olrck edge ( note 9) olrck to sdto (msb) obick ? ? to sdto tbck tbckl tbckh tlrb tblr tlrs tbsd 1/64fs 65 65 30 30 30 30 ns ns ns ns ns ns ns output (master mode) bick frequency bick duty bick ? ? to lrck bick ? ? to sdto fbck dbck tmblr tbsd ? 20 ? 20 64fs 50 20 30 hz % ns ns power-down & reset timing pdn pulse width ( note 10) tpd 150 ns note 8. min is 8khz when bypass=?h?. note 9. bick rising edge must not occur at the same time as lrck edge. note 10. the ak4121a must be reset by bringing pdn pin ?h? to ?l? upon power-up.
[ak4121a] ms0337-e-06 2010/04 - 7 - timing diagram figure 1. clock timing figure 2. audio interf ace timing at slave mode 1/fs lrck vih vil tbck tbckl vih tbckh bick vil tlrb lrck vih bick vil tlrs sdto tbsd vih vil tblr tsds sdti vih vil tsdh 70%vdd 30%vdd 1/fclk tclkl vih tclkh mclk vil dclk=tclkh x fclk, tclkl x fclk
[ak4121a] ms0337-e-06 2010/04 - 8 - lrck bick sdto tbsd tmblr 50%vdd 50%vdd 50%vdd dbck figure 3. audio interface timing at master mode figure 4. power-down & reset timing note 11. bick means ibick and obick. note 12. lrck means ilrck and olrck. tpd vil pdn vih
[ak4121a] ms0337-e-06 2010/04 - 9 - operation overview system clock the input port works in slave mode only. the output port works in slave and master mode. an internal system clock is created by the internal pll using ilrck . the mclk is not needed when the output port is in slave mode, and the mclk pin should be connected to dvss. the cmode2-0 pins must be controlled when pdn pin =?l?. mode cmode2 cmode1 cmode0 mclk master/slave (output port) 0 l l l 256fso (fso~96khz) master 1 l l h 384fso (fso~96khz) master 2 l h l 512fso (fso~48khz) master 3 l h h 768fso (fso~48khz) master 4 h l l not used. set to dvss slave 5 h l h - (reserved) 6 h h l - (reserved) 7 h h h not used. set to dvss master (bypass mode) table 1. master/slave control audio interface format the idif2-0 pins select the data mode for the input port. the odif1-0 pins select the data mode for the output port. in all modes the audio data is msb-first, 2?s compliment format . the sdto is clocked out on the falling edge of obick. select these modes when pdn pin=?l?. in bypass mode, both ibick and obick are fixed to 64fs. mode idif2 idif1 idif0 sdti format ibick (slave) 0 l l l 16bit lsb justified 32fs 1 l l h 20bit lsb justified 40fs 2 l h l 20bit msb justified 40fs 3 l h h 20/16bit i 2 s compatible 40fs or 32fs 4 h l l 24bit lsb justified 48fs table 2. input audio data formats mode odif1 odif0 sdto format obick (slave) obick (master) 0 l l 16bit lsb justified 64fs 64fs 1 l h 20bit lsb justified 64fs 64fs 2 h l 20/16bit msb justified ( note 13 ) 40fs or 32fs 64fs 3 h h 20/16bit i 2 s compatible ( note 13 ) 40fs or 32fs 64fs note 13. the 16bit output is available only when the obick = 32fs. table 3. output audio data formats
[ak4121a] ms0337-e-06 2010/04 - 10 - figure 5. 16bit/20bit lsb justified timing figure 6. 20bit msb justified timing figure 7. 20bit i 2 s timing sdti lrck bick ( 64fs ) 0 13 1 14 15 16 31 0 1 13 14 15 16 31 0 1 15 0 15 0 16bi t don?t care don?t care 15:msb, 0:lsb sdti 20bi t 19:msb, 0:lsb 16 15 0 16 15 0 don?t care don?t care 17 17 12 12 18 18 lch data rch data 19 19 lrck bick ( 64fs ) sdti 0 18 1 2 20 31 0 1 31 0 1 20:msb, 0:lsb 18 1 0 don?t care 19 lch data rch data 19 30 18 220 19 30 18 1 0 don?t care 19 18 19 lrck bick ( 64fs ) sdti 0 3 1 2 20 31 0 1 31 0 1 19:msb, 0:lsb 18 1 0 don?t care 19 lch data rch data 19 21 3 220 19 21 18 1 0 don?t care 19 19
[ak4121a] ms0337-e-06 2010/04 - 11 - soft mute operation when the smute pin changes to ?h?, the output signal is attenuated from 0db to ? db during 1024 olrck cycles. when the smute pin returns to ?l?, the attenuation is can celled and the output signal gradually changes to 0db during 1024 olrck cycles. if the soft mute is cancelled before attenuating to ? , the attenuation is discontinued and returns to 0db by the same cycles. the soft mute is effective for changing the signal source. notes: (1) transition time. 1024 olrck cycles (1024/fso). (2) if the soft mute is cancelled before attenuating to ? after starting the operation, the attenuation is discontinued and returned to 0db by the same number of clock cycles. figure 8. soft mute de-emphasis filter a digital de-emphasis filter is available for 32, 44.1 or 48 khz sampling rates (tc=50/15s) and is enabled or disabled with dem0 and dem1. mode dem1 dem0 de-emphasis filter 0 l l 44.1khz 1 l h off 2 h l 48khz 3 h h 32khz table 4. de-emphasis filter control smute 0db attenuation level at sdto - db (1) (2) (1)
[ak4121a] ms0337-e-06 2010/04 - 12 - system reset bringing the pdn pin=?l? places the ak41 21a in the power-down mode and initia lizes the digital filter. this reset should always be done after power-up. when the pdn pin = ?l?, the sdto output is ?l?. regarding the sdto valid time, please refer to the table 5 . until the output data becomes valid, the sdto pin outputs ?l?. case 1 case 2 t a external clocks (input port) sdti don?t care sdto (internal state) power-down normal operation pll lock & fs detection t b normal data (state1) external clocks (output port) don?t care don?t care pdn power-down don?t care don?t care don?t care ?0? data normal operation pll lock & fs detection (1) normal data pd (state1) (state1) (state2) (state2) (state2) ?0? data ?0? data external clocks (input port) sdti sdto (internal state) power-down normal operation pll lock & fs detection (1) normal data (no clock) external clocks (output port) pdn power-down don?t care don?t care don?t care ?0? data pll unlock (state1) (state1) (state1) ?0? data (don?t care) (don?t care) note: (1) <100ms for recommended value 2, <200ms for recommended value 1. ( figure 11 ) figure 9. system reset reset time t a data valid time t b 10ms <100ms 10ms< <200ms table 5. reset time t a and data valid time t b.
[ak4121a] ms0337-e-06 2010/04 - 13 - internal reset function for clock change the ak4121a is reset automatically when the output clock is stopped. if the output clock is started again, normal data is output within 100ms. sequence of changing clocks the recommended sequence for changing clocks is shown in figure 10 . pll lock & fs detection power-down external clocks (input port or output port) clocks 1 sdto (internal state) normal operation normal operation clocks 2 don?t care < 100ms smute (recommended) 1024/fso att.level 0db - d b normal data normal data 1024/fso pdn pin note1 note2 < 10msec figure 10. sequence of changing clocks note 1. the data on sdto may cause a clicking noise. to prevent this, set sdti to ?0? from gd before the pdn pin changes to ?l?, which will cause the data on sdto to remain ?0?. note 2. the data on sdto may cause a clicking noise. to prevent this, set sdti to ?0? for 1024/fso+100ms or more from the timing pdn pin changes to ?h? while the smute pin = ?h?. note 3. when the pdn pin is not used for this clock change, a distorted signal may output for about 10ms ~ 100ms (typ) after changing clocks.
[ak4121a] ms0337-e-06 2010/04 - 14 - grounding and power supply decoupling the ak4121a requires careful attention to power supply and grounding arrangements. vdd are usually supplied from the system?s analog supply. avss and dvss of the ak4121a must be connected to the analog ground plane. system analog ground and digital ground should be connected together as close as possib le to where the supplies are brought onto the printed circuit board. decoupling capacitors especially a 0.1 f ceramic capacitor for high frequency noise should be placed as near to vdd as possible. pll loop-filter the c1 (4.7 f) and r (560ohms) should be connected in series and attached between filt pin and avss in parallel with c2 (1.0nf). a care should be taken to ensure that noise on the filt pin is minimized. ak4121a c1 r filt a vss c2 parameter recommended value 1 recommended value 2 r 560ohm +/ ? 8% 1.2kohm +/ ? 8% c1 4.7 f +/ ? 40% 2.2 f +/ ? 40% c2 1.0nf +/ ? 40% 2.2nf +/ ? 40% fsi range 8k ~ 96khz 16k ~ 96khz note 14. those recommended values include temperature dependence. figure 11. pll loop-filter
[ak4121a] ms0337-e-06 2010/04 - 15 - jitter tolerance figure 12 shows the jitter tolerance to ilrck. the jitter quantity is defined by the jitter frequency and the jitter amplitude shown in figure 12 . when the jitter amplitude is 0.01uipp or less, the ak4121a operates normally regardless of the jitter frequency. (1) normal operation (2) there is a possibility that the distortion degrades. (it may degrade up to about ? 50db.) (3) there is a possibility that the output data is lost. note 15. the jitter amplitude for 1ui (unit interval) is on e cycle of ilrck. when fsi = 48khz, 1ui is 1/48khz = 20.8 s. figure 12. jitter tolerance tracking to the input sampling frequency when the ilrck is generated by an external pll, it may take a time to settle after changing the input sampling frequency because the response of an external pll to the fr equency change is slow. in case of the ak4121 , the output data becomes incorrect when the speed of the frequenc y change exceeds 0.14%/sec. the ak4121a oper ates normally up to 23%/sec speed and the output data becomes incorr ect at the speed of the frequency change over 23%/sec. ak4121a jitter tolerance 0.00 0.01 0.10 1.00 10.00 1 10 100 1000 10000 jitter frequency [hz] amplitude [uipp] (3) (2) (1)
[ak4121a] ms0337-e-06 2010/04 - 16 - system design figure 13 and figure 14 illustrate typical system connection diagrams. the evaluation board [akd4121a] demonstrates this application circuit, the optimum layout, and power supply arrangement and performance measurement results. filt a vss pdn smute dem0 dem1 ilrck ibick sdti idif0 idif1 idif2 vdd dvss tvdd mclk olrck obick sdto odif1 odif0 cmode2 cmode1 cmode0 ak4121a 10u + 0.1u +3.3~5v digital (*1) 0.1u dsp1 1.0n dsp2 control mode setting (fix to ?h? or ?l?) 4.7u 560 fsi fso +3.3v analog figure 13. example of a typical design (slave mode) filt a vss pdn smute dem0 dem1 ilrck ibick sdti idif0 idif1 idif2 vdd dvss tvdd mclk olrck obick sdto odif1 odif0 cmode2 cmode1 cmode0 ak4121a 10u + 0.1u +3.3~5v digital (*1) 0.1u dsp1 1.0n dsp2 control mode setting (fix to ?h? or ?l?) 4.7u 560 fsi fso +3.3v analog 64fso 256fso figure 14. example of a typical design (master mode; mclk=256fso) *1. tvdd should be the same as the maximum input voltage.
[ak4121a] ms0337-e-06 2010/04 - 17 - package 0.1 0.1 0-10 detail a seating plane note: dimension "*" does not include mold flash. 0.10 0.15 0.22 0.1 0.65 *7.9 0.2 1.25 0.2 a 1 12 13 24 24 p in vsop ( unit: mm ) 7.6 0.2 0.5 0.2 *5.6 0.2 +0.1 -0.05 package & lead frame material package molding compound: epoxy lead frame material: cu lead frame surface treatment: solder plate (pb free)
[ak4121a] ms0337-e-06 2010/04 - 18 - marking a km a k4121avf a axxx x contents of aaxxxx aa: lot# xxxx: date code
[ak4121a] ms0337-e-06 2010/04 - 19 - revision history date (yy/mm/dd) revision reason page contents 04/09/01 00 first edition 07/06/05 01 error correct 4 src performance dynamic range, worst case fso/fsi=32khz/44.1khz 48khz/96khz description change 6 switching characteristics audio interface timing ilrck edge to ibick ? ? is changed to ilrck period (8khz ~ 32khz): 1/256fs+45 ilrck period (32khz ~ 48khz): 1/256fs+25 ilrck period (48khz ~ 96khz): 1/256fs+15 07/07/25 02 description change 13 internal reset function for clock change sequence of changing clocks 07/09/14 03 add spec 6 max values of ilrck edge to ibick ? ? were added. ilrck frequency =8khz ~ 32khz: 16/256fs ilrck frequency =32khz ~ 48khz: 16/256fs ilrck frequency =48khz ~ 96khz: 16/256fs error correct 6 the symbol of ilrck edge to ibick ? ? tblr tlrb the symbol of ibick ? ? to ilrck edge tlrb tblr the symbol of olrck edge to obick ? ? tblr tlrb the symbol of obick ? ? to olrck edge tlrb tblr 08/03/05 04 description addition 9 note 13. was added. 08/04/05 05 description change 5 dc characteristics power supply current (vdd+tvdd) description was added. vdd =3.3v vdd=tvdd=3.3v vdd= 3.6v vdd=tvdd=3.6v 10/04/30 06 description addition 13 sequence of changing clocks description is added in notes.
[ak4121a] ms0337-e-06 2010/04 - 20 - important notice z these products and their specifications ar e subject to change without notice. when you consider any use or application of these product s, please make inquiries the sales office of asahi kasei microdevices corporation (akm) or authorized distributors as to current status of the products. z descriptions of external circuits, application circuits, software and other related information contained in this document are provided only to illustra te the operation and application exam ples of the semiconductor products. you are fully responsible for the incorporation of these ex ternal circuits, application circuits, software and other related information in the design of your equipments. akm assumes no responsibility for any losses incurred by you or third parties arising from the use of these inform ation herein. akm assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of such information contained herein. z any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. z akm products are neither intended nor auth orized for use as critical components note1 ) in any safety, life support, or other hazard related device or system note2 ) , and akm assumes no responsibility for such use, except for the use approved with the express written consent by representative director of akm. as used here: note1 ) a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet ve ry high standards of performance and reliability. note2 ) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medi cine, aerospace, nuclear energy, or ot her fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z it is the responsibility of the buyer or distributor of akm products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.

▲Up To Search▲

Price & Availability of AK4121A10

	To Download AK4121A10 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .